In memory designs, such as dense memory designs, a weak memory bit cell may degrade over a period of time due to various defects, such as silicon defects. For example, a device, such as a modem, may crash on aging tests because of bad bit flips on a level two (L2) cache at high temperatures. Defects caused by a weak memory cell may result in an increased number of defective parts per million (DPPM).
Single bit failures in a memory may be the result of random telegraph noise (RTN). Over a period of time, the random telegraph noise may impact the read stability of bit cells. Memory built in self test (BIST) production vectors with substantial coverage, such as one hundred percent coverage, may not identify weak bit cells at room temperature or higher. Automatic test equipment (ATE) may reproduce the failures using central processing unit (CPU) functional testing at high temperatures. The test time (e.g., approximately four seconds) for automatic test equipment is not desirable during a production flow. There is a need for improved bit cell testing to detect weak memory bit cells to reduce the number of defective parts per million.